ST STM32L4 5 Series Reference Manual page 389

RM0351
12.5.23 DMA2D IP size identification register (DMA2D_SIDR)
Address offset: 0x03FC
Reset value: 0xA3C5 DD01
31 30 29 28
15 14 13 12
Bits 31:0 SID[31:0]: Size identification
This field returns the size and identification of the DMA2D IP.
27 26 25 24
SID[31:16]
11 10 9 8
SID[15:0]
DocID024597 Rev 5
Chrom-Art Accelerator™ controller (DMA2D)
23 22 21
r
7 6 5
r
20 19 18 17
4 3 2 1
16
0
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