ST STM32L4 5 Series Reference Manual page 726

Digital filter for sigma delta modulators (DFSDM)
The regular conversions executing in continuous mode can be stopped by writing '0' to
RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the
DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh
data if converting continuously from one channel because data inside the filter is valid from
previously sampled continuous data. The speed increase depends on the chosen filter
order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by
RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is
finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
if FAST = 1 (except first conversion):
in case F
Continuous mode is not available for injected conversions. Injected conversions can be
started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to
DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is
performed, then regular continuous conversion is restarted from the next conversion cycle
(like new regular continuous conversion is applied for new channel selection - even if there
is no change in DFSDM_FLTxCR1 register).
24.4.17 Request precedence
An injected conversion has a higher precedence than a regular conversion. A regular
conversion which is already in progress is immediately interrupted by the request of an
injected conversion; this regular conversion is restarted after the injected conversion
finishes.
An injected conversion cannot be launched if another injected conversion is pending or
already in progress: any request to launch an injected conversion (either by JSWSTART or
by a trigger) is ignored as long as bit JCIP is '1' (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending
or already in progress: any request to launch a regular conversion (using RSWSTART) is
ignored as long as bit RCIP is '1' (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in
progress, the regular conversion is immediately stopped and an injected conversion is
launched. The regular conversion is then restarted and this delayed restart is signalized in
bit RPEND.
Injected conversions have precedence over regular conversions in that a injected
conversion can temporarily interrupt a sequence of continuous regular conversions. When
726/1830
x
for Sinc filters:
t = CNVCNT/f
DFSDMCLK
for FastSinc filter:
t = CNVCNT/f
DFSDMCLK
x
for Sinc and FastSinc filters:
t = CNVCNT/f
DFSDMCLK
= FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
OSR
t = I / f (... but CNVCNT=0)
OSR CKIN
DocID024597 Rev 5
= [F * (I -1 + F
OSR OSR ORD
= [F * (I -1 + 4) + 2] / f
OSR OSR
= [F * I ] / f
OSR OSR CKIN
RM0351
) + F ] / f
ORD CKIN
CKIN