Table 117. Delay Bits Versus Adc Resolution - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus

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Analog-to-digital converters (ADC)

Bit 12 Reserved, must be kept at reset value.

Bits 11:8 DELAY: Delay between 2 sampling phases

Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0,

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DUAL[4:0]: Dual ADC mode selection

Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0,

These bits are set and cleared by software. These bits are used in dual interleaved modes.

for the value of ADC resolution versus DELAY bits values.

JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

These bits are written by software to select the operating mode.

All the ADCs independent:

00000: Independent mode

00001 to 01001: Dual mode, master and slave ADCs working together

00001: Combined regular simultaneous + injected simultaneous mode

00010: Combined regular simultaneous + alternate trigger mode

00011: Combined Interleaved mode + injected simultaneous mode

00100: Reserved

00101: Injected simultaneous mode only

00110: Regular simultaneous mode only

00111: Interleaved mode only

01001: Alternate trigger mode only

All other combinations are reserved and must not be programmed

JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 117. DELAY bits versus ADC resolution

12-bit resolution

10-bit resolution

DocID024597 Rev 5

8-bit resolution

6-bit resolution

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