ST STM32L4 5 Series Reference Manual page 247

RM0351
6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res. Res.
15 14 13
DCMIE OTGFS
Res. ADCEN
N
rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGEN: Random Number Generator clock enable
Set and cleared by software.
0: Random Number Generator clock disabled
1: Random Number Generator clock enabled
Bit 17 HASHEN: HASH clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: HASH clock disabled
1: HASH clock enabled
Bit 16 AESEN: AES accelerator clock enable
Set and cleared by software.
0: AES clock disabled
1: AES clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 DCMIEN: DCMI clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: DCMI clock disabled
1: DCMI clock enabled
Bit 13 ADCEN: ADC clock enable
Set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 12 OTGFSEN: OTG full speed clock enable
Set and cleared by software.
0: USB OTG full speed clock disabled
1: USB OTG full speed clock enabled
Bits 11:9 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
EN
rw
DocID024597 Rev 5
24 23 22
Res. Res. Res. Res.
8 7 6
GPIOIE GPIOH GPIOG GPIOF
N EN EN EN
rw rw rw
Reset and clock control (RCC)
21 20 19 18
RNG
Res. Res.
EN
rw
5 4 3 2
GPIOE GPIOD GPIOC
EN EN EN
rw rw rw rw
17 16
HASHE
AESEN
N
rw rw
1 0
GPIOB GPIOA
EN EN
rw rw
247/1830
278