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Advanced-control timers (TIM1/TIM8)
30.4.22
TIM8 option register 1 (TIM8_OR1)
Address offset: 0x50
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:5 Reserved, must be kept at reset value
Bit 4 TI1_RMP: Input Capture 1 remap
Bits 3:2 ETR_ADC3_RMP: External trigger remap on ADC3 analog watchdog
Note: ADC3 AWDx sources are 'ORed' with the TIM8_ETR input signals. When ADC3 AWDx
Bits 1:0 ETR_ADC2_RMP: External trigger remap on ADC1 analog watchdog
Note: ADC2 AWDx sources are 'ORed' with the TIM8_ETR input signals. When ADC2 AWDx
30.4.23
TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3)
Address offset: 0x54
Reset value: 0x0000 0000
Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in
output.
31
30
29
Res.
Res.
Res.
Res.
966/1830
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
0: TIM8 input capture 1 is connected to I/O
1: TIM8 input capture 1 is connected to COMP2 output.
00: TIM8_ETR is not connected to ADC3 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01: TIM8_ETR is connected to ADC3 AWD1.
10: TIM8_ETR is connected to ADC3 AWD2.
11: TIM8_ETR is connected to ADC3 AWD3.
is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
00 : TIM8_ETR is not connected to ADC2 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01 : TIM8_ETR is connected to ADC2 AWD1.
10 : TIM8_ETR is connected to ADC2 AWD2.
11 : TIM8_ETR is connected to ADC2 AWD3.
is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
28
27
26
25
Res.
Res.
Res.
DocID024597 Rev 5
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
OC6M[3]
Res.
Res.
rw
20
19
18
Res.
Res.
Res.
4
3
2
TI1_
ETR_ADC3_RMP
RMP
rw
rw
rw
Figure 234: TIM8 ETR input
Figure 234: TIM8 ETR input
21
20
19
18
Res.
Res.
Res.
Res.
RM0351
17
16
Res.
Res.
1
0
ETR_ADC2_RMP
rw
rw
17
16
Res.
OC5M[3]
rw
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