ST STM32L4 5 Series Reference Manual page 980

Advanced-control timers (TIM1/TIM8)
Table 190. TIM8 register map and reset values (continued)
Offset Register
TIM8_PSC
0x28
Reset value
TIM8_ARR
0x2C
Reset value
TIM8_RCR
0x30
Reset value
TIMx_CCR1
0x34
Reset value
TIM8_CCR2
0x38
Reset value
TIM8_CCR3
0x3C
Reset value
TIM8_CCR4
0x40
Reset value
TIM8_BDTR
0x44
Reset value
TIM8_DCR
0x48
Reset value
TIM8_DMAR
0x4C
Reset value
TIM8_OR1
0x50
Reset value
TIM8_CCMR3
Output
0x54
Compare mode
Reset value
TIM8_CCR5
0x58
Reset value 0
980/1830
BK2F[3:0]
0 0 0 0
0
0 0
DocID024597 Rev 5
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
BKF[3:0]
0 0 0 0 0 0 0 0 0
0 0 0
OC6M
[2:0]
0 0 0 0
0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1 1
REP[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
LOC
K DT[7:0]
[1:0]
0 0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0 0
0
OC5M
[2:0]
0 0 0 0 0 0 0
CCR5[15:0]
0 0 0 0 0 0 0 0 0
RM0351
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
DBA[4:0]
0 0 0 0
0 0 0 0
0 0 0 0
0 0
0 0 0 0