ST STM32L4 5 Series Reference Manual page 375

RM0351
31 30 29
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15 14 13
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Bits 31: 0 MA[31: 0]: Memory address
12.5.7 DMA2D background offset register (DMA2D_BGOR)
Address offset: 0x0018
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res.
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Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line offset
28 27 26 25
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12 11 10 9
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Address of the data used for the background image. This register can only be written
when data transfers are disabled. Once a data transfer has started, this register is read-
only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
Line offset used for the background image (expressed in pixel). This value is used for
the address generation. It is added at the end of each line to determine the starting
address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
DocID024597 Rev 5
Chrom-Art Accelerator™ controller (DMA2D)
24 23 22
MA[31:16]
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8 7 6
MA[15:0]
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24 23 22 21
Res. Res. Res. Res.
8 7 6 5
LO[13:0]
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21 20 19 18
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5 4 3 2
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20 19 18
Res. Res. Res.
4 3 2
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17 16
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1 0
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17 16
Res. Res.
1 0
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