ST STM32L4 5 Series Reference Manual page 319

Advanced arm-based 32-bit mcus

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Bits 31:2 Reserved, must be kept at reset value

SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C

System reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value

Bit 1 SRAM2BSY: SRAM2 busy by erase operation

0: No SRAM2 erase operation is on going.

1: SRAM2 erase operation is on going.

Bit 0 SRAM2ER: SRAM2 Erase

Setting this bit starts a hardware SRAM2 erase operation. This bit is

automatically cleared at the end of the SRAM2 erase operation.

Note: This bit is write-protected: setting this bit is possible only after the correct

key sequence is written in the SYSCFG_SKR register.

Bit 8 SPF: SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared

by software by writing '1'.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value

Bit 3 ECCL: ECC Lock

This bit is set by software and cleared only by a system reset. It can be used to

enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input.

0: ECC error disconnected from TIM1/8/15/16/17 Break input.

1: ECC error connected to TIM1/8/15/16/17 Break input.

System configuration controller (SYSCFG)

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