Power Port A Pull-Down Control Register (Pwr_Pdcra); Power Port B Pull-Up Control Register (Pwr_Pucrb) - ST STM32L4 5 Series Reference Manual

Power control (PWR)
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 PU15: Port A pull-up bit 15
When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PD15 bit is also set.
Bit 14 Reserved, must be kept at reset value.
Bits 13:0 PUy: Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.
5.4.9

Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31 30 29
Res. Res. Res. Res.
15 14 13
Res. PD14 Res. PD12
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 PD14: Port A pull-down bit 14
When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3
register.
Bit 13 Reserved, must be kept at reset value.
Bits 12:0 PDy: Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
5.4.10

Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
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28 27 26 25
Res. Res. Res.
12 11 10 9
PD11 PD10 PD9
rw rw rw rw
DocID024597 Rev 5
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
PD8 PD7 PD6 PD5
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
PD4 PD3 PD2 PD1
rw rw rw rw
RM0351
16
Res.
0
PD0
rw