Table 165. Lcd Register Map And Reset Values - ST STM32L4 5 Series Reference Manual

RM0351
Bit 2 Reserved, must be kept at reset value
Bit 1 SOFC: Start of frame flag clear
This bit is written by software to clear the SOF flag in the LCD_SR register.
Bit 0 Reserved, must be kept at reset value
25.6.5 LCD display memory (LCD_RAM)
Address offset: 0x14 to 0x50
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 SEGMENT_DATA[31:0]
Each bit corresponds to one pixel of the LCD display.
25.6.6 LCD register map
The following table summarizes the LCD registers.
Register
LCD_CR
0x00
Reset value
LCD_FCR
0x04
Reset value
LCD_SR
0x08
Reset value
0: No effect
1: Clear SOF flag
27 26 25
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11 10 9
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0: Pixel inactive
1: Pixel active

Table 165. LCD register map and reset values

PS[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Liquid crystal display controller (LCD)
24 23 22
SEGMENT_DATA[31:16]
rw rw rw
8 7 6
SEGMENT_DATA[15:0]
rw rw rw
DIV[3:0]
DocID024597 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
0 0 0 0 0 0 0 0
CC PON
DEAD
[2:0]
[2:0] [2:0]
17 16
rw rw
1 0
rw rw
DUTY
[2:0]
0 0
1 0 0 0 0 0
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