Figure 175. 1/2 Duty, 1/2 Bias - ST STM32L4 5 Series Reference Manual

Liquid crystal display controller (LCD)
25.3.4 Segment driver
The segment driver block controls the SEG lines according to the pixel data coming from the
8 to 1 mux driven in each phase by the common driver block.
In the case of 1/4 or 1/8 duty
When COM[0] is active, the pixel information (active/inactive) related to the pixel connected
to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux.
The SEG[n] pin n [0 to 43] is driven to V
active) in phase 0 of the odd frame.
The SEG[n] pin is driven to V
SEG[n] pin is driven to 2/3 (2/4) V
(current inversion in V
In case of 1/2 bias, if the pixel is inactive the SEG[n] pin is driven to V
V in the even frame.
SS
When the LCD controller is disabled (LCDEN bit cleared in the LCD_CR register) then the
SEG lines are pulled down to V
764/1830

Figure 175. 1/2 duty, 1/2 bias

(indicating pixel n is active when COM[0] is
SS
in phase 0 of the even frame. If pixel n is inactive then the
LCD
in the odd frame or 1/3 (2/4) V
LCD
pad) (see Figure
LCD
.
SS
DocID024597 Rev 5
172).
RM0351
in the even frame
LCD
in the odd and to
LCD