ST STM32L4 5 Series Reference Manual page 275

Advanced arm-based 32-bit mcus
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RM0351
Off-
Register
set
RCC_CICR
0x20
Reset value
RCC_
AHB1RSTR
0x28
Reset value
RCC_
AHB2RSTR
0x2C
Reset value
RCC_
AHB3RSTR
0x30
Reset value
RCC_
APB1RSTR1
0x38
0 0 0 0
Reset value
RCC_
APB1RSTR2
0x3C
Reset value
RCC_
APB2RSTR
0x40
Reset value
RCC_AHB1
ENR
0x48
Reset value
Table 34. RCC register map and reset values (continued)
0 0 0 0 0 0 0 0 0 0
0
DocID024597 Rev 5
0 0
0 0 0
0 0
0 0
0 0 0
0 0
Reset and clock control (RCC)
0 0 0 0 0 0 0 0 0 0 0
0
0
0 0 0
0 0 0 0 0 0 0 0 0
0
0
0 0 0 0 0
0
1
0 0
0
0 0 0 0 0 0
0
0 0 0
0
0 0
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