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Hash processor (HASH)
HASH_HR6
Address offset: 0x328
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
HASH_HR7
Address offset: 0x32C
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
Note:
When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers are forced to their reset values.
29.6.5
HASH interrupt enable register (HASH_IMR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
872/1830
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value
Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled
DocID024597 Rev 5
24
23
22
21
H6
r
r
r
r
8
7
6
5
H6
r
r
r
r
24
23
22
21
H7
r
r
r
r
8
7
6
5
H7
r
r
r
r
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
20
19
18
17
r
r
r
r
4
3
2
1
r
r
r
r
20
19
18
17
r
r
r
r
4
3
2
1
r
r
r
r
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
DCIE
rw
RM0351
16
r
0
r
16
r
0
r
16
Res.
0
DINIE
rw
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