ST STM32L4 5 Series Reference Manual page 869

Advanced arm-based 32-bit mcus

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HASH start register (HASH_STR)

Address offset: 0x08

Reset value: 0x0000 0000

The HASH_STR register has two functions:

It is used to define the number of valid bits in the last word of the message entered in

the hash processor (that is the number of valid least significant bits in the last data

written to the HASH_DIN register)

It is used to start the processing of the last block in the message by writing the DCAL

Bits 31:9 Reserved, must be kept at reset value

Bit 8 DCAL: Digest calculation

Writing this bit to 1 starts the message padding, using the previously written

value of NBLW, and starts the calculation of the final message digest with all data

words written to the IN FIFO since the INIT bit was last written to 1.

Reading this bit returns 0.

Bits 7:5 Reserved, must be kept at reset value

Bits 4:0 NBLW: Number of valid bits in the last word

When the last word of the message bit string is written in HASH_DIN register, the

hash processor takes only the valid bits specified as below, after internal data

0x00: All 32 bits of the last data written are valid message bits i.e. M[31:0]

0x01: Only one bit of the last data written (after swapping) is valid i.e. M[0]

0x02: Only two bits of the last data written (after swapping) are valid i.e. M[1:0]

0x03: Only three bits of the last data written (after swapping) are valid i.e. M[2:0]

0x1F: Only 31 bits of the last data written (after swapping) are valid i.e. M[30:0]

The above mechanism is valid only if DCAL=0. If NBLW bits are written while

DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not

possible to configure NBLW and set DCAL at the same time.

Reading NBLW bits returns the last value written to NBLW.

DocID024597 Rev 5

Hash processor (HASH)

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