ST STM32L4 5 Series Reference Manual page 867

RM0351
Bit 3 DMAE: DMA enable
0: DMA transfers disabled
1: DMA transfers enabled. A DMA request is sent as soon as the hash core is
ready to receive data.
After this bit is set it is cleared by hardware while the last data of the message is
written to the hash processor.
Setting this bit to 0 while a DMA transfer is on-going is not aborting this current
transfer. Instead, the DMA interface of the HASH remains internally enabled until
the transfer is complete or INIT is written to 1.
Setting INIT bit to 1 does not clear DMAE bit.
Bit 2 INIT: Initialize message digest calculation
Writing this bit to 1 resets the hash processor core, so that the HASH is ready to
compute the message digest of a new message.
Writing this bit to 0 has no effect. Reading this bit always return 0.
Bits 1:0 Reserved, must be kept at reset value
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Hash processor (HASH)
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