ST STM32L4 5 Series Reference Manual page 814

Advanced arm-based 32-bit mcus

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True Random Number Generator (RNG)

RNG registers

The RNG is associated with a control register, a data register and a status register.

RNG control register (RNG_CR)

Address offset: 0x000

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value

Bit 3 IE: Interrupt Enable

Bit 2 RNGEN: True random number generator enable

Bits 1:0 Reserved, must be kept at reset value

RNG status register (RNG_SR)

Address offset: 0x004

Reset value: 0x0000 0000

0: RNG Interrupt is disabled

1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or

CEIS='1' in the RNG_SR register.

0: True random number generator is disabled. Analog noise sources are powered off and

logic clocked by the RNG clock is gated.

1: True random number generator is enabled.

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