ST STM32L4 5 Series Reference Manual page 202

Reset and clock control (RCC)
All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except:
•
The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived
(selected by software) from one of the four following sources:
–
–
–
–
When the MSI clock is auto-trimmed with the LSE, it can be used by the USB OTG FS
device.
When available, the HSI48 48 MHz clock can be coupled to the clock recovery system
allowing adequate clock connection for the USB OTG FS (Crystal less solution).
•
The ADCs clock which is derived (selected by software) from one of the three following
sources:
–
–
–
•
The U(S)ARTs clocks which are derived (selected by software) from one of the four
following sources:
–
–
–
–
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
•
The I
following sources:
–
–
–
The wakeup from Stop mode is supported only when the clock is HSI16.
•
The SAI1 and SAI2 clocks which are derived (selected by software) from one of the five
following sources:
–
–
–
–
–
•
The SWPMI1 clock which is derived (selected by software) from one of the two
following sources:
–
–
The wakeup from Stop mode is supported only when the clock is HSI16.
•
The low-power timers (LPTIMx) clock which are derived (selected by software) from
one of the five following sources:
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main PLL VCO (PLL48M1CLK)
PLLSAI1 VCO (PLL48M2CLK)
MSI clock
HSI48 internal oscillator (only for STM32L496xx/4A6xx devices)
system clock (SYSCLK)
PLLSAI1 VCO (PLLADC1CLK)
PLLSAI2 VCO (PLLADC2CLK)
system clock (SYSCLK)
HSI16 clock
LSE clock
APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the
U(S)ART)
2
Cs clocks which are derived (selected by software) from one of the three
system clock (SYSCLK)
HSI16 clock
APB1 clock (PCLK1)
an external clock mapped on SAI1_EXTCLK for SAI1 and SAI2_EXTCLK for SAI2
PLLSAI1 VCO (PLLSAI1CLK)
PLLSAI2 VCO (PLLSAI2CLK)
main PLL VCO (PLLSAI3CLK)
HSI16 clock (only for STM32L496xx/4A6xx devices)
HSI16 clock
APB1 clock (PCLK1)
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