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Analog-to-digital converters (ADC)
18.6.14
ADC regular sequence register 4 (ADC_SQR4)
Address offset: 0x3C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
18.6.15
ADC regular Data Register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 RDATA[15:0]: Regular Data converted
These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in
600/1830
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
rw
rw
These bits are written by software with the channel number (0..18) assigned as the 16th in
the regular conversion sequence.
regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 15th in
the regular conversion sequence.
regular conversion is ongoing).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
r
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
SQ16[4:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
RDATA[15:0]
r
r
r
Section 18.4.26: Data
DocID024597 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
SQ15[4:0]
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
r
r
r
r
management.
RM0351
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
r
r
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