Power Control Register 2 (Pwr_Cr2) - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus

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Power control register 2 (PWR_CR2)

Address offset: 0x04

Reset value: 0x0000 0000. This register is reset when exiting the Standby mode.

Bits 31:11 Reserved, must be kept at reset value.

Bit 8 Reserved, must be kept at reset value.

Bit 7 PVME4: Peripheral voltage monitoring 4 enable:

Bit 6 PVME3: Peripheral voltage monitoring 3 enable:

Bit 5 PVME2: Peripheral voltage monitoring 2 enable:

USB supply valid

This bit is used to validate the

Setting this bit is mandatory to use the USB OTG_FS peripheral. If

present in the application, the PVM can be used to determine whether this supply is ready or

is not present. Logical and electrical isolation is applied to ignore this supply.

Independent I/Os supply valid

This bit is used to validate the

Setting this bit is mandatory to use PG[15:2]. If

application, the PVM can be used to determine whether this supply is ready or not.

is not present. Logical and electrical isolation is applied to ignore this supply.

monitoring vs. 2.2V threshold) disable.

monitoring vs. 2.2V threshold) enable.

monitoring vs. 1.62V threshold) disable.

monitoring vs. 1.62V threshold) enable.

monitoring vs. 0.9V threshold) disable.

monitoring vs. 0.9V threshold) enable.

PVME4 PVME3 PVME2 PVME1

supply for electrical and logical isolation purpose.

supply for electrical and logical isolation purpose.

DocID024597 Rev 5

Power control (PWR)

is not always present in the

is not always

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