ST STM32L4 5 Series Reference Manual page 972

Advanced-control timers (TIM1/TIM8)
Bit 0 BK2INE: BRK2 BKIN input enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Refer to
30.4.28 TIM8 option register 2 (TIM8_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
ETRSEL[1:0] Res. Res.
rw rw
Bits 31:17 Reserved, must be kept at reset value
Bits 16:14 ETRSEL[2:0]: ETR source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:12 Reserved, must be kept at reset value
Bit 11 BKCMP2P: BRK COMP2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BKCMP1P: BRK COMP1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
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This bit enables the BKIN2 alternate function input for the timer's BRK2 input. BKIN2 input is
'ORed' with the other BRK2 sources.
0: BKIN2 input disabled
1: BKIN2 input enabled
in TIMx_BDTR register).
Figure 255: Break and Break2 circuitry
27 26 25
Res. Res. Res.
11 10 9
BKCM BKCM
BKINP
P2P P1P
rw rw rw
These bits select the ETR input source.
000: TIM8_ETR is selected with the ETR_ADC3_RMP and ETR_ADC2_RMP bitfield in
TIM8_OR1 register
001: COMP1 output connected to ETR input
010: COMP2 output connected to ETR input
others: Reserved
bits in TIMx_BDTR register).
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input is active high
1: COMP2 input is active low
in TIMx_BDTR register).
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP1 input is active high
1: COMP1 input is active low
in TIMx_BDTR register).
overview.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BKDF1
Res. Res. Res.
BK2E
rw
DocID024597 Rev 5
20 19 18
Res. Res. Res.
4 3 2
BKCMP2 BKCMP
Res. Res.
E
rw
RM0351
17 16
ETRSEL
Res.
[2]
rw
1 0
BKINE
1E
rw rw