Table 155. Dfsdm Break Connection - ST STM32L4 5 Series Reference Manual

RM0351
dfsdm_jtrg9
dfsdm_jtrg10
dfsdm_break[0]
dfsdm_break[1]
dfsdm_break[2]
dfsdm_break[3]
24.4.3 DFSDM reset and clocks
DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7)
and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel
enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in
DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the
DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sinc
filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDM_FLTx is put into stop mode. All register settings remain unchanged except
DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.
Once the channel is enabled, it receives serial data from the external Σ∆ modulator or
parallel internal data sources (ADCs
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before
stopping the system clock to enter in the STOP mode of the device.
DFSDM clocks
The internal DFSDM clock f
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK (max. up to f
peripheral clock PCLK2 (see DFSDMSEL bit description in
independent clock configuration register
stopped in stop mode (if DFEN = 0 for all DFSDM_FLTx, x=0..3).
a. STM32L496xx/4A6xx devices only.
Table 154. DFSDM triggers connection (continued)
Trigger name

Table 155. DFSDM break connection

Break name
(a)
, which is used to drive the channel transceivers,
DFSDMCLK
DocID024597 Rev 5
Digital filter for sigma delta modulators (DFSDM)
EXTI11
EXTI15
Break destination
TIM1 break
TIM1 break2
TIM8 break
TIM8 break2
or CPU/DMA wire from memory).
Section 6.4.28: Peripherals
(RCC_CCIPR)). The DFSDM clock is automatically
Trigger source
x
digital
= 80 MHz) or
SYSCLK
705/1830
756