ST STM32L4 5 Series Reference Manual page 198

Power control (PWR)
Offset Register
PWR_PDCRE
0x044
Reset value
PWR_PUCRF
0x048
Reset value
PWR_PDCRF
0x04C
Reset value
PWR_PUCRG
0x050
Reset value
PWR_PDCRG
0x054
Reset value
PWR_PUCRH
0x058
Reset value
PWR_PDCRH
0x05C
Reset value
PWR_PUCRI
0x060
Reset value
PWR_PDCRI
0x064
Reset value
Refer toSection 2.2.2: Memory map and register boundary addresses
boundary addresses.
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Table 32. PWR register map and reset values (continued)
DocID024597 Rev 5
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
for the register
RM0351
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0