ST STM32L4 5 Series Reference Manual page 624

Digital-to-analog converter (DAC)
Note: 1 In the above formula the settling to the desired code value with ½ LSB or accuracy requires
10 constant time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant
time.
2 The tolerated voltage drop during the hold phase "Vd" is represented by the number of LSBs
after the capacitor discharging with the output leakage current. The settling back to the
desired value with ½ LSB error accuracy requires ln(2*Nlsb) constant time of the DAC.
3 The parameters "T
Example of the sample and refresh time calculation with output buffer on
Note: The values used in the example below are provided as indication only. Please refer to the
product datasheet for product data.
C = 100 nF
load
V = 3.0 V
DDA
Sampling phase:
t
sampling
(where T
Refresh phase:
t
refresh
(where N
Hold phase:
D = i
v
i
leak
t
hold
624/1830
","T
stab-BON stab-BOFF
= 7 μs + (10 * 2000 * 100 * 10
= 7 μs, RBON = 2 kΩ)
stab-BON
= 7 μs + (2000 * 100 * 10
= 10 (10 LSB drop during the hold phase)
lsb
* t / C = 0.0073 V (10 LSB of 12bit at 3 V)
leak hold load
= 150 nA (worst case on the IO leakage on all the temperature range)
-9
= 0.0073 * 100 * 10
DocID024597 Rev 5
", "R " and "R
BON BOFF
-9
) = 2.007 ms
-9
) * ln(2*10) = 606.1 μs
-9
/ (150 * 10 ) = 4.867 ms
" are specified in the datasheet
RM0351