ST STM32L4 5 Series Reference Manual page 257

RM0351
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Reset value: 0x0007 73FF (for STM32L496xx/4A6xx devices)
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
ADC
DCMIS OTGFS
Res.
MEN SMEN
SMEN
rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop
modes
1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop
modes
Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: HASH clocks disabled by the clock gating
1: HASH clocks enabled by the clock gating
Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating
1: AES clocks enabled by the clock gating
Bits 15 Reserved, must be kept at reset value.
Bit 14 DCMISMEN: DCMI clock enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: DCMI clocks disabled by the clock gating
1: DCMI clocks enabled by the clock gating
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating
1: ADC clocks enabled by the clock gating
0x0005 32FF (for STM32L475xx/476xx/486xx devices)
28 27 26 25
Res. Res. Res.
12 11 10 9
SRAM2
Res. Res.
SMEN
rw rw
DocID024597 Rev 5
24 23 22
Res. Res. Res. Res.
8 7 6
GPIOIS GPIOH GPIOG GPIOF
MEN SMEN SMEN SMEN
rw rw rw
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
Reset and clock control (RCC)
21 20 19 18
RNG
Res. Res.
SMEN
rw
5 4 3 2
GPIOE GPIOD GPIOC
SMEN SMEN SMEN
rw rw rw rw
17 16
AES
HASHS
MEN
SMEN
rw rw
1 0
GPIOB GPIOA
SMEN SMEN
rw rw
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