Table 107. Adc1, Adc2 And Adc3 - External Triggers For Regular Channels; Figure 78. Triggers Are Shared Between Adc Master And Adc Slave - ST STM32L4 5 Series Reference Manual

Analog-to-digital converters (ADC)
Note: The regular trigger selection cannot be changed on-the-fly.
The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 18.4.21: Queue of context for injected conversions on page 528
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 78.
Table 107
and injected conversion.

Table 107. ADC1, ADC2 and ADC3 - External triggers for regular channels

Name
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT8
EXT9
524/1830

Figure 78. Triggers are shared between ADC master and ADC slave

and Table 108 give all the possible external triggers of the three ADCs for regular
Source
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_TRGO
TIM4_CH4
EXTI line 11
TIM8_TRGO
TIM8_TRGO2
TIM1_TRGO
DocID024597 Rev 5
Type
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
External pin
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
RM0351
EXTSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001