Table of Contents
Advertisement
Digital-to-analog converter (DAC)
19.5.2
DAC software trigger register (DAC_SWTRGR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
Bit 0 SWTRIG1: DAC channel1 software trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
19.5.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
19.5.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
636/1830
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
register value has been loaded into the DAC_DOR2 register.
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
register value has been loaded into the DAC_DOR1 register.
27
26
25
Res.
Res.
Res.
11
10
9
rw
rw
rw
These bits are written by software which specifies 12-bit data for DAC channel1.
DocID024597 Rev 5
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
DACC1DHR[11:0]
rw
rw
rw
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
rw
rw
rw
rw
RM0351
17
16
Res.
Res.
1
0
SWTRIG2 SWTRIG1
w
w
17
16
Res.
Res.
1
0
rw
rw
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32L4 5 Series and is the answer not in the manual?