ST STM32L4 5 Series Reference Manual page 265

RM0351
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating
1: USART1clocks enabled by the clock gating
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 timer clocks disabled by the clock gating
1: TIM8 timer clocks enabled by the clock gating
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during
1: SPI1 clocks enabled by the clock gating during
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 timer clocks disabled by the clock gating
1: TIM1P timer clocks enabled by the clock gating
Bit 10 SDMMC1SMEN: SDMMC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC clocks disabled by the clock gating
1: SDMMC clocks enabled by the clock gating
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating
Stop modes
1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating
Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.28 Peripherals independent clock configuration register (RCC_CCIPR)
Address: 0x88
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
SWP
DFSDM
MI1
1 ADCSEL[1:0]
SEL
SEL
rw rw rw
15 14 13
I2C2SEL[1:0] I2C1SEL[1:0]
rw rw rw
28 27 26 25
CLK48SEL[1:0] SAI2SEL[1:0]
rw rw rw rw
12 11 10 9
LPUART1SEL UART5SEL
[1:0]
rw rw rw rw
DocID024597 Rev 5
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
(1)
(1)
(1)
during Sleep and Stop modes
24 23 22
SAI1SEL[1:0]
rw rw rw
8 7 6
UART4SEL
[1:0] [1:0]
rw rw rw
Reset and clock control (RCC)
during Sleep and Stop modes
during Sleep and Stop modes
(1)
Sleep and Stop modes
(1)
Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and
(1)
during Sleep and
21 20 19
LPTIM2SEL[1:0] LPTIM1SEL[1:0
rw rw rw
5 4 3
USART3SEL USART2SEL
[1:0] [1:0]
rw rw rw
18 17 16
I2C3SEL[1:0]
rw rw rw
2 1 0
USART1SEL
[1:0]
rw rw rw
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