Table 102. Main Adc Features - ST STM32L4 5 Series Reference Manual

RM0351
–
•
Start-of-conversion can be initiated:
–
–
•
Conversion modes
–
–
–
–
•
Dual ADC mode for ADC1 and 2
•
Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular
or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or
3 or overrun events
•
3 analog watchdogs per ADC
•
ADC supply requirements: 1.62 to 3.6 V
•
ADC input range: V
Figure 66
18.3 ADC implementation
Dual mode
DFSDM interface
SMPPLUS control
1. Available only on STM32L496xx/STM32L4A6xx.
DAC1 and DAC2 internal channels, connected to ADC2 and ADC3
by software for both regular and injected conversions
by hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
Each ADC can convert a single channel or can scan a sequence of channels
Single mode converts selected inputs once per trigger
Continuous mode converts selected inputs continuously
Discontinuous mode
≤ V
REF–
shows the block diagram of one ADC.

Table 102. Main ADC features

References
(1)
(1)
DocID024597 Rev 5
Analog-to-digital converters (ADC)
≤ V
IN REF+
ADC1 ADC2 ADC3
X X
X X
X X
503/1830
X
X
X
614