ST STM32L4 5 Series Reference Manual page 865

RM0351
29.6 HASH registers
The HASH core is associated with several control and status registers and five message
digest registers. All these registers are accessible through 32-bit word accesses only, else
an AHB2 error is generated.
29.6.1 HASH control register (HASH_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. MDMAT DINNE
rw
Bits 31:19 Reserved, must be kept at reset value
28 27 26 25
Res. Res. Res.
12 11 10 9
NBW
r r r r
Bit 18 ALGO[1]: refer to bit 7 description
Bit 17 Reserved, must be kept at reset value
Bit 16 LKEY: Long key selection
This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC
mode.
0: Short key (≤ 64 bytes)
1: Long key (> 64 bytes)
Note: This selection is only taken into account when the INIT bit is set and
MODE= 1. Changing this bit during a computation has no effect.
Bit 15 Reserved, must be kept at reset value
Bit 14 Reserved, must be kept at reset value
Bit 13 MDMAT: Multiple DMA Transfers
This bit is set when hashing large files when multiple DMA transfers are needed.
0: DCAL is automatically set at the end of a DMA transfer.
1: DCAL is not automatically set at the end of a DMA transfer.
Bit 12 DINNE: DIN not empty
This bit is set when the HASH_DIN register holds valid data (that is after being
written at least once). It is cleared when either the INIT bit (initialization) or the
DCAL bit (completion of the previous message processing) is written to 1.
0: No data are present in the data input buffer
1: The input buffer contains at least one word of data
DocID024597 Rev 5
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
ALGO[0] MODE DATATYPE
r rw rw rw
Hash processor (HASH)
20 19 18 17
Res. Res. ALGO[1] Res.
rw
4 3 2 1
DMAE INIT Res.
rw rw w
16
LKEY
rw
0
Res.
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