ST STM32L4 5 Series Reference Manual page 404

Extended interrupts and events controller (EXTI)
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
14.5.5 Software interrupt event register 1 (EXTI_SWIER1)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
SWI SWI SWI SWI
15 14 13
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22: 18 SWIx: Software interrupt on line x (x = 22 o 18)
Bits 16:0 SWIx: Software interrupt on line x (x = 16 to 0)
404/1830
28 27 26 25
Res. Res. Res.
12 11 10 9
SWI SWI SWI
12 11 10 9
rw rw rw rw
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by
writing a '1' into the bit).
Bit 17 Reserved, must be kept at reset value.
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
into the bit).
DocID024597 Rev 5
24 23 22 21
SWI SWI
Res. Res.
22 21
rw rw
8 7 6 5
SWI SWI SWI SWI
8 7 6 5
rw rw rw rw
20 19 18 17
SWI SWI SWI
Res.
20 19 18
rw rw rw
4 3 2 1
SWI SWI SWI SWI
4 3 2 1
rw rw rw rw
RM0351
16
SWI
16
rw
0
SWI
0
rw