ST STM32L4 5 Series Reference Manual page 231

RM0351
6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR)
Address offset: 0x14
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI2 clock outputs according to the formulas:
• f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLM)
• f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2P
• f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R
31 30 29
PLLSAI2PDIV[4:0]
rw rw rw
15 14 13
Res.
rw rw
Bits 31:27 PLLSAI2PDIV[4:0]: PLLSAI2 division factor for PLLSAI2CLK (only on STM32L496xx/4A6xx
devices)
Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI2CLK output
clock
frequency = VCOSAI2 frequency / PLLSAI2PDIV.
00000: PLLSAI2CLK is controlled by the bit PLLSAI2P
00001: Reserved.
00010: PLLSAI2CLK = VCOSAI2 / 2
....
11111: PLLSAI2CLK = VCOSAI2 / 31
Bits 26:25 PLLSAI2R[1:0]: PLLSAI2 division factor for PLLADC2CLK (ADC clock)
Bit 24 PLLSAI2REN: PLLSAI2 PLLADC2CLK output enable
Bits 23:18 Reserved, must be kept at reset value.
28 27 26 25
PLLSAI2R[1:0]
rw rw rw rw
12 11 10 9
PLLSAI2N[6:0]
rw rw rw rw
Set and cleared by software to control the frequency of the SAI2PLL output clock
PLLADC2CLK. This output can be selected as ADC clock. These bits can be written only if
SAI2PLL is disabled.
PLLADC2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2R with PLLSAI2R =
2, 4, 6, or 8
00: PLLSAI2R = 2
01: PLLSAI2R = 4
10: PLLSAI2R = 6
11: PLLSAI2R = 8
Set and reset by software to enable the PLLADC2CLK output of the SAI2PLL (used as clock
for ADC).
In order to save power, when the PLLADC2CLK output of the SAI2PLL is not used, the value
of PLLSAI2REN should be 0.
0: PLLADC2CLK output disable
1: PLLADC2CLK output enable
24 23 22
PLL
PLL
SAI2 Res.
SAI2Q
REN
rw
8 7 6
Res. Res.
rw
DocID024597 Rev 5
Reset and clock control (RCC)
21 20 19 18
PLL
SAI2 Res. Res.
QEN
5 4 3 2
Res. Res. Res. Res.
17 16
PLL
PLL
SAI2
SAI2P
PEN
rw rw
1 0
Res. Res.
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