Figure 209. Hash Save/Restore Mechanism - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0351
30313233 34353637 38393A3B 3C3D3E3F
2.
Message input (lenght=34, i.e. padding required). HASH_STR must be set to 0x20 to
start message padding and inner hash computation (see
53616D70 6C65206D 65737361 67652066 6F72206B 65796C65
6E3D626C 6F636B6C
3.
Outer hash key input (lenght=64, i.e. no padding). A key identical to the inner hash key
is entered here.
4.
Final outer hash computing is then performed by the HASH. The HMAC-SHA1 is
available in the HASH_Hx registers (x = 0...4), as shown below:
HASH_H0 = 0x5FD596EE
HASH_H1 = 0x78D5553C
HASH_H2 = 0x8FF4E72D
HASH_H3 = 0x266DFD19
HASH_H4 = 0x2366DA29
29.3.8
Context swapping
Overview
It is possible to interrupt a hash/HMAC operation to perform another processing with a
higher priority. The interrupted process completes later when the higher-priority task has
been processed, as shown in
To do so, the context of the interrupted task must be saved from the HASH registers to
memory, and then be restored from memory to the HASH registers.
The procedures where the data flow is controlled by software or by DMA are described
below.
656EUUUU
Figure
209.

Figure 209. HASH save/restore mechanism

DocID024597 Rev 5
Hash processor (HASH)
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861/1830
875

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