Table 97. Fmc Register Map - ST STM32L4 5 Series Reference Manual

Flexible static memory controller (FSMC)
16.7 FMC register map
Offset Register
FMC_BCR1
0x00
Reset value
FMC_BCR2
0x08
Reset value
FMC_BCR3
0x10
Reset value
FMC_BCR4
0x18
Reset value
FMC_BTR1
0x04
Reset value
FMC_BTR2
0x0C
Reset value
FMC_BTR3
0x14
Reset value
FMC_BTR4
0x1C
Reset value
FMC_BWTR1
0x104
Reset value
FMC_BWTR2
0x10C
Reset value
470/1830

Table 97. FMC register map

0
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
0 0 1 1 1 1 1 1 1
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
0 0 1 1 1 1 1 1 1
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
0 0 1 1 1 1 1 1 1
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
0 0 1 1 1 1 1 1 1
0 0
0 0
DocID024597 Rev 5
CPSIZE
[2:0]
0 0 0 0 0 0 0 1
CPSIZE
[2:0]
0 0 0 0 0 0 1
CPSIZE
[2:0]
0 0 0 0 0 0 1
CPSIZE
[2:0]
0 0 0 0 0 0 1
DATAST[7:0]
1 1 1 1 1 1 1 1
DATAST[7:0]
1 1 1 1 1 1 1 1
DATAST[7:0]
1 1 1 1 1 1 1 1
DATAST[7:0]
1 1 1 1 1 1 1 1
BUSTURN[3:0] DATAST[7:0]
1 1 1 1 1 1 1
BUSTURN[3:0] DATAST[7:0]
1 1 1 1 1 1 1
MWID
[1:0]
1 0 0 0 1 0
MWID
[1:0]
1 0 0 0 1 0
MWID
[1:0]
1 0 0 0 1 0
MWID
[1:0]
1 0 0 0 1 0
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
RM0351
MTYP
[1:0]
1 1 0 1 1
MTYP
[1:0]
1 0 0 1 0
MTYP
[1:0]
1 0 0 1 0
MTYP
[1:0]
1 0 0 1 0
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1