Table 152. Dfsdm External Pins; Table 153. Dfsdm Internal Signals; Table 154. Dfsdm Triggers Connection - ST STM32L4 5 Series Reference Manual

Digital filter for sigma delta modulators (DFSDM)
STM32L496xx/4A6xx devices.
24.4.2 DFSDM pins and internal signals
Name
VDD
VSS
CKIN[7:0]
DATIN[7:0]
CKOUT
EXTRG[1:0]
dfsdm_jtrg[10:0]
dfsdm_break[3:0]
dfsdm_dma[3:0]
dfsdm_it[3:0]
dfsdm_dat_adc[15:0]
1. STM32L496xx/4A6xx devices only.
dfsdm_jtrg0
dfsdm_jtrg1
dfsdm_jtrg2
dfsdm_jtrg3
dfsdm_jtrg4
dfsdm_jtrg5
dfsdm_jtrg6
dfsdm_jtrg7
dfsdm_jtrg8
704/1830

Table 152. DFSDM external pins

Signal Type
Power supply
Power supply
Clock input
Data input
Clock output
External trigger
signal

Table 153. DFSDM internal signals

Name Signal Type
Internal/
external
trigger signal
break signal
output
DMA request
signal
Interrupt
request signal
ADC input
(1)
data

Table 154. DFSDM triggers connection

Trigger name
DocID024597 Rev 5
Digital power supply.
Digital ground power supply.
Clock signal provided from external Σ∆ modulator. FT input.
Data signal provided from external Σ∆ modulator. FT input.
Clock output to provide clock signal into external Σ∆
modulator.
Input trigger from two EXTI signals to start analog
conversion (from GPIOs: EXTI11, EXTI15).
Input trigger from internal/external trigger sources to start
analog conversion, see
Break signals event generation from Analog watchdog or
short-circuit detector
DMA request signal from each DFSDM_FLTx (x=0..3):
end of injected conversion event.
Interrupt signal for each DFSDM_FLTx (x=0..3)
Up to 4 internal ADC data buses as parallel inputs.
TIM1_TRGO
TIM1_TRGO2
TIM8_TRGO
TIM8_TRGO2
TIM3_TRGO
TIM4_TRGO
TIM16_OC1
TIM6_TRGO
TIM7_TRGO
Remarks
Remarks
Table 154 for details.
Trigger source
RM0351