Figure 179. Lcd Voltage Control - ST STM32L4 5 Series Reference Manual

Liquid crystal display controller (LCD)
1. R and R
LN
The R
LN
register (see
The HD switch follows the rules described below:
•
If the HD bit and the PON[2:0] bits in the LCD_FCR register are reset, then HD switch
is open.
•
If the HD bit in the LCD_FCR register is reset and the PON[2:0] bits in the LCD_FCR
are different from 00 then, the HD switch is closed during the number of pulses defined
in the PON[2:0] bits.
•
If HD bit in the LCD_FCR register is 1 then HD switch is always closed.
Buffered mode
When voltage output buffers are enabled by setting BUFEN bit in the LCD_CR register, LCD
driving capability is improved as buffers prevent the LCD capacitive loads from loading the
resistor bridge unacceptably and interfering with its voltage generation. As a result we
obtain more stable intermediate voltage levels thus improving RMS voltage applied to the
LCD pixels.
770/1830

Figure 179. LCD voltage control

are the low value resistance network and the high value resistance network, respectively.
HN
divider can be always switched on using the HD bit in the LCD_FCR configuration
Section 25.6.2).
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