Table 90. Fmc_Bcrx Bit Fields; Figure 55. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram) - ST STM32L4 5 Series Reference Manual

RM0351

Figure 55. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit number
31-22
21
20
19
18:16
15
14

Table 90. FMC_BCRx bit fields

Bit name
Reserved 0x000
As needed (this bit is reserved for STM32L475xx/476xx/486xx
WFDIS
devices)
CCLKEN As needed
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
DocID024597 Rev 5
Flexible static memory controller (FSMC)
Value to set
449/1830
471