ST STM32L4 5 Series Reference Manual page 251

RM0351
Bit 19 UART4EN: UART4 clock enable
Bit 18 USART3EN: USART3 clock enable
Bit 17 USART2EN: USART2 clock enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Bit 14 SPI2EN: SPI2 clock enable
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Bit 10 RTCAPBEN: RTC APB clock enable (This bit is reserved for STM32L475xx/476xx/486xx
devices)
Bit 9 LCDEN: LCD clock enable
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: UART4 clock disabled
1: UART4 clock enabled
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Set by software to enable the window watchdog clock. Reset by hardware system reset.
This bit can also be set by hardware if the WWDG_SW option bit is reset.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Set and cleared by software
0: RTC APB clock disabled
1: RTC APB clock enabled
Set and cleared by software.
0: LCD clock disabled
1: LCD clock enabled
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
DocID024597 Rev 5
Reset and clock control (RCC)
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