ST STM32L4 5 Series Reference Manual page 499

RM0351
17.6.12 QUADSPI polling interval register (QUADSPI _PIR)
Address offset: 0x002C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31: 16 Reserved, must be kept at reset value.
Bits 15: 0 INTERVAL[15: 0]: Polling interval
17.6.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
Address offset: 0x0030
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31: 16 Reserved, must be kept at reset value.
Bits 15: 0 TIMEOUT[15: 0]: Timeout period
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
INTERVAL[15:0]
rw rw rw rw
Number of CLK cycles between to read during automatic polling phases.
This field can be written only when BUSY = 0.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
TIMEOUT[15:0]
rw rw rw rw
After each access in memory-mapped mode, the QUADSPI prefetches the subsequent
bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the
QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash
memory in a lower-consumption state.
This field can be written only when BUSY = 0.
DocID024597 Rev 5
Quad-SPI interface (QUADSPI)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
rw rw rw rw
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
rw rw rw rw
19 18 17 16
Res. Res. Res. Res.
3 2 1
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