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Reset and clock control (RCC)
Bit 2 GPIOCRST: IO port C reset
Bit 1 GPIOBRST: IO port B reset
Bit 0 GPIOARST: IO port A reset
6.4.12
AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x30
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIRST: QUADSPI1 memory interface reset
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
6.4.13
APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
240/1830
Set and cleared by software.
0: No effect
1: Reset IO port C
Set and cleared by software.
0: No effect
1: Reset IO port B
Set and cleared by software.
0: No effect
1: Reset IO port A
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
Set and cleared by software.
0: No effect
1: Reset QUADSPI
Set and cleared by software.
0: No effect
1: Reset FMC
24
23
22
Res.
Res.
Res.
8
7
6
QSPI
Res.
Res.
RST
rw
DocID024597 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0351
17
16
Res.
Res.
1
0
FMC
Res.
RST
rw
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