Table of Contents
Advertisement
Flexible static memory controller (FSMC)
Table 71. NOR Flash/PSRAM: example of supported memories and transactions
Device
PSRAM
(multiplexed
I/Os and non-
multiplexed
I/Os)
SRAM and
ROM
16.5.3
General timing rules
Signals synchronization
•
All controller output signals change on the rising edge of the internal clock (HCLK)
•
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
426/1830
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.
DocID024597 Rev 5
AHB
Memory
R/W
data
data size
size
R
8
16
W
8
16
R
16
16
W
16
16
R
32
16
W
32
16
R
-
16
R
8
16
R
16
16
R
32
16
W
8
16
W
16/32
16
R
8 / 16
16
W
8 / 16
16
R
32
16
W
32
16
Allowed/
not
Comments
allowed
Y
Y
Use of byte lanes NBL[1:0]
Y
Y
Y
Split into 2 FMC accesses
Y
Split into 2 FMC accesses
N
Mode is not supported
N
Y
Y
Y
Use of byte lanes NBL[1:0]
Y
Y
Y
Use of byte lanes NBL[1:0]
Y
Split into 2 FMC accesses
Split into 2 FMC accesses
Y
Use of byte lanes NBL[1:0]
RM0351
-
-
-
-
-
-
-
-
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32L4 5 Series and is the answer not in the manual?