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ST STM32F74 Series Getting Started

ST STM32F74 Series Getting Started

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Getting started with STM32F74xxx/STM32F75xxx MCU hardware
Introduction
This application note is intended for system designers who require an hardware
implementation overview of the development board, with focus on features:
•
Power supply,
•
Package selection,
•
Clock management,
•
Reset control,
•
Boot mode settings,
•
Debug management.
This document describes the minimum hardware resources required to develop an
application based on the STM32F74xxx/STM32F75xxx devices.
Microcontrollers
June 2015
Table 1. Applicable products
Type
STM32F745IE, STM32F745VE, STM32F745IG, STM32F745VG,
STM32F745ZE, STM32F745ZG
STM32F746VG, STM32F746ZG, STM32F746IG, STM32F746BG,
STM32F746NG, STM32F746IE, STM32F746VE, STM32F746ZE,
STM32F746BE, STM32F746NE
STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG
DocID027559 Rev 2
Application note
development
Part number
AN4661
1/45
www.st.com
1

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Summary of Contents for ST STM32F74 Series

  • Page 1 STM32F74xxx/STM32F75xxx devices. Table 1. Applicable products Type Part number STM32F745IE, STM32F745VE, STM32F745IG, STM32F745VG, STM32F745ZE, STM32F745ZG STM32F746VG, STM32F746ZG, STM32F746IG, STM32F746BG, Microcontrollers STM32F746NG, STM32F746IE, STM32F746VE, STM32F746ZE, STM32F746BE, STM32F746NE STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG June 2015 DocID027559 Rev 2 1/45 www.st.com...

  • Page 2: Table Of Contents

    Contents AN4661 Contents Power supplies ..........7 Introduction .
  • Page 3 AN4661 Contents SWJ debug port (serial wire and JTAG) ......23 Pinout and debug port pins ........23 5.3.1 SWJ debug port pins .
  • Page 4 Contents AN4661 8.5.2 WLCSP143 0.4 mm pitch design example ..... . 41 Conclusion ..........43 Revision history .
  • Page 5 AN4661 List of tables List of tables Table 1. Applicable products ............1 Table 2.
  • Page 6 List of figures AN4661 List of figures Figure 1. VDDUSB connected to VDD power supply ........8 Figure 2.

  • Page 7: Power Supplies

    AN4661 Power supplies Power supplies Introduction The device requires a 1.8 to 3.6 V operating voltage supply (V ), which can be reduced down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear voltage regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V voltage when the main V...

  • Page 8: Battery Backup Domain

    Power supplies AN4661 Figure 1. V connected to V power supply DDUSB Figure 2. V connected to external power supply. DDUSB 1.1.3 Battery backup domain Backup domain description To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when is turned off, V pin can be connected to an optional standby voltage supplied by a battery or by another source.

  • Page 9: Voltage Regulator

    AN4661 Power supplies When the backup domain is supplied by V (analog switch connected to V because is not present), the following functions are available: • PC14 and PC15 can be used as LSE pins only. • PC13 can be used as tamper pin (TAMP1). •...

  • Page 10: Figure 3. Power Supply Scheme

    Power supplies AN4661 connected on this pin. In all cases, V must be kept between (V -1.2 V) and REF+ with minimum of 1.7 V. • Additional precautions can be taken to filter analog noise: – can be connected to V through a ferrite bead.

  • Page 11: Reset & Power Supply Supervisor

    AN4661 Power supplies μF) must be connected. 2. V is either connected to V or to V (depending on package). REF+ REF+ 3. V is either connected to V or to V (depending on package). REF- REF- 4. 19 is the number of V and V inputs.

  • Page 12: System Reset

    Power supplies AN4661 A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to indicate if V is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V drops below the PVD threshold and/or when V...

  • Page 13: Internal Reset On

    AN4661 Power supplies Figure 6. Reset circuit 1.3.4 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. For more details about the internal reset ON, refer to the datasheets (DS10915, DS10916). 1.3.5 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin.

  • Page 14: Regulator Off Mode

    Power supplies AN4661 The supply ranges which never go below 1.8V minimum should be better managed by the internal circuitry (no additional component needed, thanks to the fully embedded reset controller). When the internal reset is OFF, the following integrated features are no more supported: •...

  • Page 15: Figure 9. Bypass_Reg Supervisor Reset Connection

    AN4661 Power supplies logic power domain (V PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. • In regulator OFF mode, the following features are no more supported: – PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.

  • Page 16: Regulator On/Off And Internal Reset On/Off Availability

    Power supplies AN4661 1.3.7 Regulator ON/OFF and internal reset ON/OFF availability Table 2. Regulator ON/OFF and internal reset ON/OFF availability Internal reset Package Regulator ON Regulator OFF Internal reset ON LQFP100 LQFP144, LQFP208 LQFP176, PDR_ON set to PDR_ON set to WLCSP143, BYPASS_REG set BYPASS_REG set...

  • Page 17: Alternate Function Mapping To Pins

    Alternate function mapping to pins Alternate function mapping to pins In order to easily explore peripheral alternate functions mapping to pins it is recommended to use the STM32CubeMX tool available on www.st.com. Figure 10. STM32CubeMX example screen-shot DocID027559 Rev 2...

  • Page 18: Clocks

    Clocks AN4661 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator clock. • HSE oscillator clock. • Main PLL (PLL) clock. The devices have the two following secondary clock sources: • 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.

  • Page 19: External Crystal/Ceramic Resonator (Hse Crystal)

    AN4661 Clocks 3.1.2 External crystal/ceramic resonator (HSE crystal) The external oscillator frequency ranges from 4 to 26 MHz. The external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 12.

  • Page 20: External Clock (Lse Bypass)

    Clocks AN4661 The LSE oscillator includes new modes and has a configurable drive using the LSEDRV [1:0] in RCC_BDCR register: • 00: Low drive. • 10: Medium low drive. • 01: Medium high drive. • 11: High drive. The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not.

  • Page 21: Boot Configuration

    – Boot address defined by user option byte BOOT_ADD0[15:0] BOOT_ADD0 [15:0] - ST programmed value: Flash on ITCM at 0x0020 0000 – Boot address defined by user option byte BOOT_ADD1[15:0] BOOT_ADD1 [15:0] - ST programmed value: System bootloader at 0x0010 0000...

  • Page 22: Boot Pin Connection

    1. Resistor values are given only as a typical example. System bootloader mode The embedded bootloader code is located in system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces.

  • Page 23: Debug Management

    AN4661 Debug management Debug management Introduction The host/target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool. Figure 16 shows the connection of the host to the evaluation board.

  • Page 24: Swj Debug Port Pins

    Debug management AN4661 5.3.1 SWJ debug port pins Five pins are used as outputs from the STM32F74xxx/STM32F75xxx for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages. Table 5. SWJ debug port pins JTAG debug port SW debug port SWJ-DP pin name assignment...

  • Page 25: Internal Pull-Up And Pull-Down On Jtag Pins

    AN4661 Debug management 5.3.3 Internal pull-up and pull-down on JTAG pins It is necessary to ensure that the JTAG input pins are not floating since they are directly connected to flip-flops to control the debug mode features. A special care must be taken with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.

  • Page 26: Recommendations

    Recommendations AN4661 Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.

  • Page 27: Other Signals

    AN4661 Recommendations Figure 18. Typical layout for V pair Other signals When designing an application, the EMC performance can be improved by closely studying: • Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands).

  • Page 28: Reference Design

    Reference design AN4661 Reference design Description The reference design shown in Figure 19, is based on the STM32F756NGH6, a highly ® integrated microcontroller running at 216 MHz, that combines the Cortex -M7 32-bit RISC CPU core with 1 Mbyte of embedded Flash memory and system SRAM up to 320 Kbytes (including Data TCM RAM 64 Kbytes), 16 Kbytes of instruction RAM (ITCM-RAM) and 4 Kbytes of backup SRAM.

  • Page 29: Component References

    AN4661 Reference design Component references Table 7. Mandatory components Component name Reference Quantity Comments Microcontroller STM32F756NGH6 TFBGA216 package Ceramic capacitors Capacitor 100 nF (decoupling capacitors) Ceramic capacitor Capacitor 4.7 µF (decoupling capacitor) Table 8. Optional components Components Reference Quantity Comments name Pull-up and pull-down for JTAG, BOOT pin, PDR and Resistor...

  • Page 30: Figure 19. Stm32F756Ngh6 Reference Schematic

    Reference design AN4661 Figure 19. STM32F756NGH6 reference schematic 30/45 DocID027559 Rev 2...

  • Page 31: Table 9. Reference Connection For All Packages

    AN4661 Reference design Table 9. Reference connection for all packages Pin Name PA13 (JTMS-SWDIO) PA14 (JTCK-SWCLK) PA15 (JTDI) PB3 (JTDO/TRACESWO) PB4 (NJTRST) (1)(2) PC14 (PC14-OSC32_IN) (1)(2) PC15 (PC15-OSC32_OUT) PH0 (PH0-OSC_IN) PH1 (PH1-OSC_OUT) BOOT NRST BYPASS_REG PDR_ON REF+ REF- CAP1 CAP2 DDUSB DocID027559 Rev 2 31/45...
  • Page 32 Reference design AN4661 Table 9. Reference connection for all packages (continued) Pin Name PA0-WKUP PC13 32/45 DocID027559 Rev 2...
  • Page 33 AN4661 Reference design 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF.

  • Page 34: Recommended Pcb Routing Guidelines For Stm32F745Xx/Stm32F756Xx Devices

    Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices PCB stack-up In order to reduce the reflections on high speed signals, it is necessary to match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.

  • Page 35: Crystal Oscillator

    AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices Figure 21. Six layer PCB stack-up example Crystal oscillator Use the application note: Oscillator design guide for STM8S, STM8A and STM32 microcontrollers (AN2867), for further guidance on how to layout and route crystal oscillator circuits.

  • Page 36: High Speed Signal Layout

    Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices AN4661 Figure 22. Example of bypass cap placed underneath the STM32F74xxx/STM32F75xxx • Place the bypass capacitors as close as possible to the power and ground pins of the MCU. • Add the recommended bypass capacitors for as many V /GND pairs as possible.

  • Page 37: Flexible Memory Controller (Fmc) Interface

    AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices Interface signal layout guidelines: • Reference the plane using GND or PWR (if PWR, add 10nf switching cap between PWR and GND) • Trace the impedance: 50Ω ± 10% • The skew being introduced into the clock system by unequal trace lengths and loads, minimize the board skew, keep the trace lengths equal between the data and clock.

  • Page 38: Quadrature Serial Parallel Interface (Quad Spi)

    Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices AN4661 Interface signal layout guidelines: • Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND • Trace the impedance: 50Ω ± 10% • The maximum trace length should be below 120mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used •...

  • Page 39: Embedded Trace Macrocell (Etm)

    AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices Avoid using a serpentine routing for the clock signal and as less via(s) as possible for the whole path. a via alter the impedance and add a reflection to the signal. 8.4.4 Embedded trace macrocell (ETM) Interface connectivity The ETM enables the reconstruction of the program execution.

  • Page 40: Figure 23. Bga 0.8Mm Pitch Example Of Fan-Out

    Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices AN4661 Figure 23. BGA 0.8mm pitch example of fan-out Figure 24. Via fan-out Figure 25. FMC signal fan-out routing example 40/45 DocID027559 Rev 2...

  • Page 41: Table 11. Wafer Level Chip Scale Package Information

    AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices 8.5.2 WLCSP143 0.4 mm pitch design example Table 11. Wafer level chip scale package information Package information (mm) Design parameters (mm) Microvia size : hole size ∅= 0.1, via land: 0.2 Bump pitch : 0.4 Bump size : 0.25 Trace width/space : 0.07/0.05 or 0.07/0.07 Number of rows/columns : 13x11...

  • Page 42: Figure 26. 143-Bumps Wlcsp, 0.40 Mm Pitch Routing Example

    Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices AN4661 Figure 26. 143-bumps WLCSP, 0.40 mm pitch routing example 42/45 DocID027559 Rev 2...
  • Page 43 AN4661 Conclusion Conclusion This application note should be used as a starting reference for a new design with STM32F74xxx and STM32F75xxx devices. DocID027559 Rev 2 43/45...

  • Page 44: Table 1. Applicable Products

    Revision history AN4661 Revision history Table 12. Document revision history Date Revision Changes 24-Mar-2015 Initial release. Added Section 8: Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices. Updated title and the whole document changing STM32F746xx/STM32F756xx by STM32F74xxx/STM32F75xxx. Updated Table 1: Applicable products adding STM32F745xx RPNs.
  • Page 45 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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