ST STM32L4 5 Series Reference Manual page 974

Advanced-control timers (TIM1/TIM8)
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value
Bit 11 BK2CMP2P: BRK2 COMP2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BK2CMP1P: BRK2 COMP1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 9 BK2INP: BRK2 BKIN2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 8 BK2DF1BK3E: BRK2 dfsdm1_break[3] enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bits 7:3 Reserved, must be kept at reset value
Bit 2 BK2CMP2E: BRK2 COMP2 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 1 BK2CMP1E: BRK2 COMP1 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
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11 10 9
BK2C BK2C BK2IN BK2DF1
MP2P MP1P P
rw rw rw
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2
polarity bit.
0: COMP2 input is active low
1: COMP2 input is active high
in TIMx_BDTR register).
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2
polarity bit.
0: COMP1 input is active low
1: COMP1 input is active high
in TIMx_BDTR register).
This bit selects the BKIN2 alternate function input sensitivity. It must be programmed
together with the BKP2 polarity bit.
0: BKIN2 input is active low
1: BKIN2 input is active high
in TIMx_BDTR register).
This bit enables the dfsdm1_break[3] for the timer's BRK2 input. dfsdm1_break[3] output is
'ORed' with the other BRK2 sources.
0: dfsdm1_break[3] input disabled
1: dfsdm1_break[3] input enabled
in TIMx_BDTR register).
This bit enables the COMP2 for the timer's BRK2 input. COMP2 output is 'ORed' with the
other BRK2 sources.
0: COMP2 input disabled
1: COMP2 input enabled
in TIMx_BDTR register).
This bit enables the COMP1 for the timer's BRK2 input. COMP1 output is 'ORed' with the
other BRK2 sources.
0: COMP1 input disabled
1: COMP1 input enabled
in TIMx_BDTR register).
DocID024597 Rev 5
8 7 6 5
Res. Res. Res.
BK3E
rw
4 3 2
BK2CMP BK2CM
Res. Res.
2E
rw
RM0351
1 0
BK2INE
P1E
rw rw