Figure 232. External Trigger Input Block; Figure 233. Tim1 Etr Input Circuitry - ST STM32L4 5 Series Reference Manual

RM0351
30.3.4 External trigger input
The timer features an external trigger input ETR. It can be used as:
•
external clock (external clock mode 2, see
•
trigger for the slave mode (see
•
PWM reset input for cycle-by-cycle current regulation (see
Figure 232
ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed
by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.
The ETR input comes from multiple sources: input pins (default configuration), comparator
outputs and analog watchdogs. The selection is done with:
• the ETRSEL[2:0] bitfield in the TIMx_OR2 register
•
the ETR_ADC1_RMP bitfield in the TIMxOR1[1:0] register
• the ETR_ADC3_RMP bitfield in the TIMxOR1[3:2] register.
below describes the ETR input conditioning. The input polarity is defined with the

Figure 232. External trigger input block

Figure 233. TIM1 ETR input circuitry

DocID024597 Rev 5
Advanced-control timers (TIM1/TIM8)
Section 30.3.5)
Section 30.3.26)
Section 30.3.7)
893/1830
981