ST STM32L4 5 Series Reference Manual page 370

Chrom-Art Accelerator™ controller (DMA2D)
12.5 DMA2D registers
12.5.1 DMA2D control register (DMA2D_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. CEIE CTCIE
rw
Bits 31:18 Reserved, must be kept at reset value
Bits 17:16 MODE[1:0]: DMA2D mode
Bits 15:14 Reserved, must be kept at reset value
Bit 13 CEIE: Configuration Error Interrupt Enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
Bit 10 TWIE: Transfer watermark interrupt enable
Bit 9 TCIE: Transfer complete interrupt enable
370/1830
28 27 26 25
Res. Res. Res.
12 11 10 9
CAEIE TWIE TCIE
rw rw rw rw
These bits are set and cleared by software. They cannot be modified while a transfer is
ongoing.
00: Memory-to-memory (FG fetch only)
01: Memory-to-memory with PFC (FG fetch only with FG PFC active)
10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
11: Register-to-memory (no FG nor BG, only output stage active)
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
This bit is set and cleared by software.
0: TW interrupt disable
1: TW interrupt enable
This bit is set and cleared by software.
0: TC interrupt disable
1: TC interrupt enable
DocID024597 Rev 5
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TEIE Res. Res. Res.
rw
20 19 18 17
Res. Res. Res. MODE[1:0]
rw
4 3 2 1
Res. Res. ABORT SUSP
rs rw
RM0351
16
rw
0
START
rs