S3, S4: Dma-Bus; S5: Dma2D-Bus; Busmatrix - ST STM32L4 5 Series Reference Manual

RM0351
bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the external memories through the QUADSPI or the FMC.
On STM32L496xx/4A6xx devices, the SRAM2 is also accessible on this bus to allow
continuous mapping with SRAM1.
2.1.4

S3, S4: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this
bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2
peripherals, the AHB2 peripherals and the external memories through the QUADSPI or the
FMC.
2.1.5

S5: DMA2D-bus

This bus connects the AHB master interface of the DMA2D to the BusMatrix. The targets of
this bus are the SRAM1 and SRAM2 and external memories through the QUADSPI or the
FMC.
2.1.6

BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of up to six masters (CPU AHB,
system bus, DCode bus, ICode bus, DMA1, DMA2 and DMA2D bus) and up to eight slaves
(FLASH, SRAM1, SRAM2, AHB1 (including APB1 and APB2), AHB2, QUADSPI and FMC).
AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses, allowing flexible selection of the peripheral frequency.
Refer to
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
a. it is present on L496/L4A6 only
(a)
Section 2.2.2: Memory map and register boundary addresses on page 75
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