ST STM32L4 5 Series Reference Manual page 358

Chrom-Art Accelerator™ controller (DMA2D)
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Area filling with a fixed color
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Copy from an area to another
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Copy with pixel format conversion between source and destination images
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Copy from two sources with independent color format and blending
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Abort and suspend of DMA2D operations
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Watermark interrupt on a user programmable destination line
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Interrupt generation on bus error or access conflict
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Interrupt generation on process completion
12.3 DMA2D functional description
12.3.1 General description
The DMA2D controller performs direct memory transfer. As an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
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Register-to-memory
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Memory-to-memory
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Memory-to-memory with Pixel Format Conversion
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Memory-to-memory with Pixel Format Conversion and Blending
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in
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Figure 32: DMA2D block
DocID024597 Rev 5
RM0351
diagram.