ST STM32L4 5 Series Reference Manual page 605

RM0351
18.6.21 ADC Differential mode Selection Register (ADC_DIFSEL)
Address offset: 0xB0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16.
These bits are read only. These channels are forced to single-ended input mode (either connected to
a single-ended I/O port or to an internal channel).
Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1
These bits are set and cleared by software. They allow to select if a channel is configured as single
ended or differential mode.
DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode
DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
It is mandatory to keep cleared ADC1_DIFSEL[15] (connected to an internal single ended
channel)
Bit 0 DIFSEL[0]: Differential mode for channel 0
This bit is read only. This channel is forced to single-ended input mode (connected to an internal
channel).
18.6.22 ADC Calibration Factors (ADC_CALFACT)
Address offset: 0xB4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
DIFSEL[15:0]
rw rw rw
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
DocID024597 Rev 5
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res.
r
5 4 3 2
rw rw rw rw
21 20 19 18
CALFACT_D[6:0]
rw rw rw rw
5 4 3 2
CALFACT_S[6:0]
rw rw rw rw
17 16
DIFSEL[18:16]
r r
1 0
rw r
17 16
rw rw
1 0
rw rw
605/1830
614