ST STM32L4 5 Series Reference Manual page 255

RM0351
Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 TIM8EN: TIM8 timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bit 10 SDMMC1EN: SDMMC clock enable
Set and cleared by software.
0: SDMMC clock disabled
1: SDMMC clock enabled
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 FWEN: Firewall clock enable
Set by software, reset by hardware. Software can only write 1. A write at 0 has no effect.
0: Firewall clock disabled
1: Firewall clock enabled
Bits 6:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF clock enable
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clock disabled
1: SYSCFG + COMP + VREFBUF clock enabled
6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR)
Address offset: 0x68
Reset value: 0x0003 1303 (for STM32L496xx/4A6xx devices)
Access: no wait state, word, half-word and byte access
0x0001 1303 (for STM32L475xx/476xx/486xx devices)
DocID024597 Rev 5
Reset and clock control (RCC)
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