ST STM32L4 5 Series Reference Manual page 385

RM0351
12.5.16 DMA2D output memory address register (DMA2D_OMAR)
Address offset: 0x003C
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31: 0 MA[31: 0]: Memory Address
28 27 26 25
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12 11 10 9
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Address of the data used for the output FIFO. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
DocID024597 Rev 5
Chrom-Art Accelerator™ controller (DMA2D)
24 23 22 21
MA[31:16]
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8 7 6 5
MA[15:0]
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20 19 18 17
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4 3 2 1
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16
rw
0
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