Figure 172. 1/3 Bias, 1/4 Duty - ST STM32L4 5 Series Reference Manual

RM0351
addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined
as:
f = f
BLINK
with BLINKF[2:0] = 0, 1, 2, ... ,7
The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
25.3.3 Common driver
Common signals are generated by the common driver block (see
COM signal bias
Each COM signal has identical waveforms, but different phases. It has its max amplitude
V or V
LCD
phases, the signal amplitude is:
• 1/4 V
•
1/3 V
•
and 1/2 V
Selection between 1/2, 1/3 and 1/4 bias mode can be done through the BIAS bits in the
LCD_CR register.
A pixel is activated when both of its corresponding common and segment lines are active
during the same phase, it means when the voltage difference between common and
segment is maximum during this phase. Common signals are phase inverted in order to
reduce EMI. As shown in
V at the end of every odd cycle.
LCD
In case of 1/2 bias (BIAS = 01) the VLCD pin generates an intermediate voltage equal to 1/2
V on node b for odd and even frames (see
LCD
COM signal duty
Depending on the DUTY[2:0] bits in the LCD_CR register, the COM signals are generated
with static duty (see
duty (see
(BLINKF + 3)
/2 ,
ck_div
only in the corresponding phase of a frame cycle, while during the other
SS
or 3/4 V in case of 1/4 bias
LCD LCD
or 2/3 V in case of 1/3 bias
LCD LCD
in case of 1/2 bias.
LCD
Figure

Figure 172. 1/3 bias, 1/4 duty

Figure 174), 1/2 duty (see
Figure 177) or 1/8 duty (see
DocID024597 Rev 5
Liquid crystal display controller (LCD)
172, with phase inversion, there is a mean voltage of 1/2
Figure 175).
Figure 175), 1/3 duty (see
Figure 178).
Figure 171).
Figure 176), 1/4
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